The present invention relates to a circuit for removing noise in a data input operation of a memory device. More particularly, the present invention relates to an apparatus for processing a signal in a memory device and a circuit for removing noise such as a glitch or notch occurring in a data input signal.
A NAND flash memory device includes a memory cell array, a row decoder and a page buffer.
The memory cell array has a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and cell strings corresponding to the bit lines.
A column decoder connected to a string select line, the word lines and a common source line is disposed at one side of the memory cell array. The page buffer connected to the bit lines is located at another side of the memory cell array.
A chip is formed by packaging the flash memory device with surrounding circuits that are needed for operation of the flash memory device. Data, an operation command and power, etc., are input through pads connected to a connection pin of the chip.
FIG. 1 is a block diagram illustrating a partial data signal input circuit included in a conventional flash memory device. The data signal input circuit processes a write enable WE signal for inputting data to the flash memory device.
In FIG. 1, the data signal input circuit 100 includes a WE pad 110 for receiving the WE signal for inputting data, an input buffering section 120 for buffering the WE signal provided from the WE pad 110 and outputting a digital signal WESYNC_N, a clock generator 130 for outputting an address counter synchronizing signal CK4CNT (Clock for Count) and a command interface synchronizing signal CK4CI (Clock for Command interface) in accordance with the signal WESYNC_N output from the input buffering section 120, an address counter 140 for receiving the synchronizing signal CK4CNT from the clock generator 130 and counting an address using the received synchronizing signal CK4CNT, and a command interface section 150 for receiving the synchronizing signal CK4CI from the clock generator 130 and providing an interface for performing a command.
The WE pad section 110 is connected to the connection pin of the chip for receiving the WE signal, and transmits the received WE signal to the input buffering section 120.
The input buffering section 120 buffers the WE signal transmitted from the WE pad section 120, and amplifies the buffered WE signal to a digital level, and outputs the amplified WE signal, i.e. signal WESYNC_N.
The clock generator 130 receives the signal WESYNC_N from the input buffering section 120, and outputs the signals CK4CNT and CK4CI using the received signal WESYNC_N.
The address counter 140 and the command interface section 150 output a control signal for controlling an data input operation so that input data is synchronized with a clock in accordance with the signals CK4CNT and CK4CI.
In the data signal input circuit 100, noise may occur in the WE signal input through the WE pad 110 due to, for example, outside interference.
FIG. 2A is a timing diagram illustrating an output signal of the input buffering section when a notch occurs in the WE signal of FIG. 1.
Referring to FIG. 1 and FIG. 2A, the notch may occur in the WE signal input through the WE pad section 110.
The notch 210 is referred to as a ring back phenomenon, and may occur for any of various reasons.
The input buffering section 120 amplifies the input WE signal to a digital level, and outputs the amplified WE signal. Particularly, as shown in FIG. 2A, the input buffering section 120 generally outputs the signal WESYNC_N having a high level when the WE signal has a voltage greater than an upper voltage VIH, and outputs the signal VESYNC_N having a low level when the WE signal has a voltage less than a lower voltage VIL.
Accordingly, a level of the WE signal to which the notch phenomenon occurs as shown in FIG. 2A is converted to a high level when the WE signal is increased to a voltage more than the upper voltage VIH, and is converted to a low level when the WE signal is decreased to a voltage less than the lower voltage VIL.
The level of the WE signal in FIG. 2A is converted from a high level to a low level and then converted from a low level to a high level to enable data input.
The notch occurs to the WE signal when the WE signal is converted from a high level to a low level and when the WE signal is converted from a low level to a high level. As a result, the input buffering section 120 outputs the signal WESYNC_N as shown in FIG. 2A.
However, the level of the normal WE signal should be converted from a high level to a low level for a certain time, and then converted from a low level to a high level.
FIG. 2B is a timing diagram illustrating the output signal of the input buffering section when a glitch phenomenon occurs to the WE signal of FIG. 1.
In FIG. 1 and FIG. 2B, the glitch phenomenon may occur to the WE signal input through the WE pad section 110.
The WE signal which should be maintained at a high level is instantaneously decreased to a voltage less than the lower voltage VIL and is then increased to a voltage greater than the lower voltage VIL due to the glitch phenomenon 220.
As a result, the input buffering section 120 outputs the signal WESYNC_N which is decreased from a high level to a low level and is then increased to a high level. However, a level of the normal signal WESYNC_N is constantly maintained at a high level.
The notch phenomenon or the glitch phenomenon is noise generated when impedance mismatching of a channel or a power drop occurs on a printed circuit board (PCB) packaged in the chip.
When the notch phenomenon or the glitch phenomenon occurs to the WE signal, as shown in FIG. 2A and FIG. 2B, the input buffering section 120 outputs a signal different from the normal signal WESYNC_N. Since the notch phenomenon or the glitch phenomenon causes a malfunction of the chip, it is important to remove the noise such as caused by the notch and the glitch.